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description the A6211 is a single ic switching regulator that provides constant-current output to drive high-power leds. it integrates a high-side n-channel dmos switch for dc-to-dc step- down (buck) conversion. a true average current is output using a cycle-by-cycle, controlled on-time method. output current is user-selectable by an external current sense resistor. output voltage is automatically adjusted to drive various numbers of leds in a single string. this ensures the optimal system efficiency. led dimming is accomplished by a direct logic input pulse width modulation (pwm) signal at the enable pin. the device is provided in a compact 8-pin narrow soic package (suffix lj) with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. A6211-ds features and benefits ? supply voltage 6 to 48 v ? true average output current control ? 3.0 a maximum output over operating temperature range ? cycle-by-cycle current limit ? integrated mosfet switch ? dimming via direct logic input or power supply voltage ? internal control loop compensation ? undervoltage lockout (uvlo) and thermal shutdown protection ? low power shutdown (1 a typical) ? robust protection against: ? adjacent pin-to-pin short ? pin-to-gnd short ? component open/short faults constant-current 3-ampere pwm dimmable buck regulator led driver package 8-pin soicn with exposed thermal pad (suffix lj): applications: ? general illumination ? scanners and multi-function printers (light bars) ? architectural lighting ? industrial lighting ? display case lighting / mr16 typical application circuit not to scale A6211 c1 r1 gnd vin v in (6 to 48 v) 1 2 3 4 8 7 6 5 sw gnd vcc A6211 boot ton en cs c5 c4 d1 l1 led + led ? rsense en enable/pwm dimming (100 hz to 2 khz) . . .
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit supply voltage v in ?0.3 to 50 v bootstrap drive voltage v boot ?0.3 to v in + 8 v switching voltage v sw ?1.5 to v in + 0.3 v linear regulator terminal v cc vcc to gnd ?0.3 to 14 v enable and ton voltage v en , v ton ?0.3 to v in + 0.3 v current sense voltage v cs ?0.3 to 7 v operating ambient temperature t a g temperature range ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?65 to 125 oc selection guide part number operating ambient temperature, t a package packing A6211gljtr-t ?40oc to 105oc 8-pin soicn with exposed thermal pad 3000 pieces per 13-in reel thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance, junction to ambient r ja 4-layer pcb based on jedec standard 35 oc/w package thermal resistance, junction to pad r jp 2 oc/w *additional thermal information available on the allegro website. pin-out diagram terminal list table number name function 1 vin supply voltage input terminals 2 ton regulator on-time setting resistor terminal 3 en logic input for enable and pwm dimming 4 cs drive output current sense feedback 5 vcc internal linear regulator output 6 gnd ground terminal 7 boot dmos gate driver bootstrap terminal 8 sw switched output terminals ?pad exposed pad for enhanced thermal dissipation; connect to gnd sw boot gnd vcc vin ton en cs 1 2 3 4 8 7 6 5 pad
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com + ? + ? + ? v il = 0.4 v v ih = 1.8 v 0.2 v boot cvcc cboot l1 d1 led string vcc shutdown vin v in c comp en ton r on cs gnd rsense sw on-time current generator on-time timer ic and driver control logic level shift gate drive uvlo v cc uvlo off-time timer v reg 5.3 v + ? buck switch current sense current limit off-time timer i lim thermal shutdown v cc uvlo pad average functional block diagram
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at v in = 24 v, for t a = ?40c to 105c, typical values at t a = 25c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit input supply voltage v in t a = 25c 6 ? 48 v v in undervoltage lockout threshold v uvlo v in increasing ? 5.3 ? v v in undervoltage lockout hysteresis v uvlo _ hys v in decreasing ? 150 ? mv vin pin supply current i in v cs = 0.5 v, en = high ? 5 ? ma vin pin shutdown current i insd en shorted to gnd ? 1 10 a boot switch current limit threshold i swlim 3.0 4.0 5.0 a buck switch on-resistance r ds(on) v boot = v in + 4.3 v, t a = 25c, i sw = 1 a ? 0.25 0.4 boot undervoltage lockout threshold v bootuv v boot to v sw increasing 1.7 2.9 4.3 v boot undervoltage lockout hysteresis v botuvhys v boot to v sw decreasing ? 370 ? mv switching minimum off-time t offmin v cs = 0 v ? 110 150 ns switching minimum on-time t onmin ? 110 150 ns selected on-time t on v in = 24 v, v out = 12 v, r on = 137 k 800 1000 1200 ns regulation comparator and error amplifier load current sense regulation threshold v csreg v cs decreasing, sw turns on 187.5 200 210 mv load current sense bias current i csbias v cs = 0.2 v, en = low ? 0.9 ? a internal linear regulator vcc regulated output v cc 0 ma < i cc < 5 ma, v in > 6 v 5.0 5.3 5.6 v vcc current limit* i cclim v in = 24 v, v cc = 0 v 5 20 ? ma enable input logic high voltage v ih v en increasing 1.8 ? ? v logic low voltage v il v en decreasing ? ? 0.4 v en pin pull-down resistance r enpd v en = 5 v ? 100 ? k maximum pwm dimming off-time t pwml measured while en = low, during dimming control, and internal references are powered-on (exceeding t pwml results in shutdown) 10 17 ? ms thermal shutdown thermal shutdown threshold t sd ? 165 ? c thermal shutdown hysteresis t sdhys ?25?c *the internal linear regulator is not designed to drive an external load
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance panel 1b. v in = 24 v panel 1c. v in = 30 v panel 1a. v in = 19 v t c1,c2 c3 c4 v in v out i led v en figure 1. startup waveforms from off-state at various input voltages; note that the rise time of the led current depends on input/output voltages, inductor value, and switching frequency ? operating conditions: led voltage = 15 v, led current = 1.3 a, r 1 = 63.4 k (frequency = 1 mhz in steady state), v in = 19 v (panel 1a), 24 v (panel 1b) and 30 v (panel 1c) ? oscilloscope settings: ch1 (red) = v in (10 v/div), ch2 (blue) = v out (10 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 50 s/div t c1,c2 c3 c4 v in v out i led v en t c1,c2 c3 c4 v in v out i led v en
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t t figure 2. pwm operation at various duty cycles; note that there is no startup delay during pwm dimming operation ? operating conditions: at 200 hz, v in = 24 v, v out = 15 v, r1 = 63.4 k , duty cycle = 50% (panel 2a) and 2% (panel 2b) ? ch1 (red) = v in (10 v/div), ch2 (blue) = v out (10 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 1 ms/div (panel 2a) and 50 s/div (panel 2b) panel 2a. duty cycle = 50% and time scale = 1 ms/div panel 2b. duty cycle = 2% and time scale = 50 s/div c1,c2 c1,c2 c3 c3 c4 c4 v in v in v out v out i led i led v en v en
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 95 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency, h (%) led current, i led (a) v in = 24 v, v out = 15 v v in = 12 v, v out = 5.5 v v in = 12 v, v out = 3.5 v 95 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency, h (%) led current, i led (a) f sw = 500 khz f sw = 1 mhz f sw = 2 mhz 1 0.1 0.01 0.001 0.1 100 110 duty cycle (%) led current (a) i led = 3 a i led = 2 a i led = 1.4 a figure 3. efficiency versus led current at various led voltages operating conditions: f sw = 1 mhz figure 4. efficiency versus led current at various switching frequencies operating conditions: v in = 12 v, v out = 5.5 v figure 5. average led current versus pwm dimming percentage operating conditions: v in = 12 v, v out = 3.5 v, f sw = 1 mhz, f pwm = 200 hz, l = 10 h
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A6211 is a buck regulator designed for driving a high-current led string. it utilizes average current mode control to maintain constant led current and consistent brightness. the led current level is easily programmable by selection of an external sense resistor, with a value determined as follows: i led = v csreg / r sense where v csreg = 0.2 v typical. switching frequency the A6211 operates in fixed on-time mode during switching. the on-time (and hence switching frequency) is programmed using an external resistor connected between the vin and ton pins, as given by the following equation: t on = k ( r on + r int ) ( v out / v in ) f sw = 1 / [ k ( r on + r int )] where k = 0.0139, with f sw in mhz, t on in s, and r on and r int (internal resistance, 5 k ) in k (see figure 6). enable and dimming the ic is activated when a logic high signal is applied to the en (enable) pin. the buck converter ramps up the led current to a target level set by rsense. when the en pin is forced from high to low, the buck converter is turned off, but the ic remains in standby mode for up to 10 ms. if en goes high again within this period, the led current is turned on immediately. active dimming of the led is achieved by sending a pwm (pulse-width modulation) signal to the en pin. the resulting led brightness is proportional to the duty cycle ( t on / period ) of the pwm signal. a practical range for pwm dimming frequency is between 100 hz ( period = 10 ms) and 2 khz. at a 200 hz pwm frequency, the dimming duty cycle can be varied from 100% down to 1% or lower. if en is low for more than 17 ms, the ic enters shutdown mode to reduce power consumption. the next high signal on en will initialize a full startup sequence, which includes a startup delay of approximately 130 s. this startup delay is not present during pwm operation. the en pin is high-voltage tolerant and can be directly connected to a power supply. however, if en is higher than the v in voltage functional description figure 6. switching frequency versus r ton resistance figure 7. simplified buck controller equations, and reference circuit and waveforms 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 f sw (mhz) r ton (k ) ? during sw on-time: i ripple = [( v in ? v out ) / l ] t on = [( v in ? v out ) / l ] t d i ripple = [( v out ? v d ) / l ] t off = [( v out ? v d ) / l ] t (1 ? d ) v out = v in d ? v d (1 ? d ) v out = ( v in ? i av r ds(on) ) d ? v d (1 ? d ) ? r l i av where d = t on / t. where r l is the resistance of the inductor. ? during sw off-time: therefore (simplified equation for output voltage): more precisely: if v d << v out , then v out v in d. v sw i l t t v in i(max) i av i(min) 0 i ripple t on t off t ?v d c in vin A6211 sw v out rsense l i l mos d
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com at any time, a series resistor (1 k ) is required to limit the current flowing into the en pin. this series resistor is not necessary if en is driven from a logic input. pwm dimming ratio the brightness of the led string can be reduced by adjusting the pwm duty cycle at the en pin as follows: dimming ratio = pwm on-time / pwm period for example, by selecting a pwm period of 5 ms (200 hz pwm frequency) and a pwm on-time of 50 s, a dimming ratio of 1% can be achieved. in an actual application, the minimum dimming ratio is deter- mined by various system parameters, including: v in , v out , inductance, led current, switching frequency, and pwm frequency. as a general guideline, the minimum pwm on-time should be kept at 50 s or longer. a shorter pwm on-time is acceptable under more favorable operating conditions. output voltage and duty cycle figure 7 provides simplified equations for approximating output voltage. essentially, the output voltage of a buck converter is approximately given as: v out = v in d ? v d1 (1 ? d ) v in d , if v d1 << v in d = t on / ( t on + t off ) where d is the duty cycle, and v d1 is the forward drop of the schottky diode d1 (typically under 0.5 v). minimum and maximum output voltages for a given input voltage, the maximum output voltage depends on the switching frequency and minimum t off . for example, if t off (min) = 150 ns and f sw = 1 mhz, then the maximum duty cycle is 85%. so for a 24 v input, the maximum output is 20.3 v. this means up to 6 leds can be operated in series, assuming v f = 3.3 v or less for each led. the minimum output voltage depends on minimum t on and switching frequency. for example, if the minimum t on = 150 ns and f sw = 1 mhz, then the minimum duty cycle is 15%. that means with v in = 24 v, the minimum v out = 3.2 v (one led). to a lesser degree, the output voltage is also affected by other factors such as led current, on-resistance of the high-side switch, dcr of the inductor, and forward drop of the low-side diode. the more precise equation is shown in figure 7. as a general rule, switching at lower frequencies allows a wider range of v out , and hence more flexible led configurations. this is shown in figure 8. figure 8 shows how the minimum and maximum output volt- ages vary with led current (assuming r ds(on) = 0.4 , inductor dcr = 0.1 , and diode v f = 0.6 v). if the required output voltage is lower than that permitted by the minimum t on , the controller will automatically extend the t off , in order to maintain the correct duty cycle. this means that the switching frequency will drop lower when necessary, while the led current is kept in regulation at all times. figure 8. minimum and maximum output voltage versus switching frequency (v in = 24 v, i led = 2 a, minimum t on and t off = 150 ns) figure 9. minimum and maximum output voltage versus i led current (v in = 9 v, f sw = 1 mhz, minimum t on and t off = 150 ns) 24 22 20 18 16 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v out ( v ) f sw (mhz) v out (max) (v) v out (min) (v) 9 8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v out ( v ) i led (a) v out (max) (v) v out (min) (v)
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal budgeting the A6211 is capable of supplying a 3 a current through its high-side switch. however, depending on the duty cycle, the conduction loss in the high-side switch may cause the package to overheat. therefore care must be taken to ensure the total power loss of package is within budget. for example, if the maximum temperature rise allowed is ? t = 50 k at the device case surface, then the maximum power dissipation of the ic is 1.4 w. assum- ing the maximum r ds(on) = 0.4 and a duty cycle of 85%, then the maximum led current is limited to 2 a approximately. at a lower duty cycle, the led current can be higher. fault handling the A6211 is designed to handle the following faults: ? pin-to-ground short ? pin-to-neighboring pin short ? pin open ? external component open or short ? output short to gnd the waveform in figure 10 illustrates how the A6211 responds in the case in which the current sense resistor or the cs pin is shorted to gnd. note that the sw pin overcurrent protection is tripped at around 3.75 a, and the part shuts down immediately. the part then goes through startup retry after approximately 380 s of cool-down period. component selections the inductor is often the most critical component in a buck con- verter. follow the procedure below to derive the correct param- eters for the inductor: 1. determine the saturation current of the inductor. this can be done by simply adding 20% to the average led current: i sat i led 1.2 . 2. determine the ripple current amplitude (peak-to-peak value). as a general rule, ripple current should be kept between 10% and 30% of the average led current: 0.1 < i ripple(pk-pk) / i led < 0.3 . 3. calculate the inductance based on the following equations: l = ( v in ? v out ) d t / i ripple , and d = ( v out + v d1 ) / ( v in + v d1 ) , where d is the duty cycle, t is the period 1/ f sw , and v d1 is the forward voltage drop of the schottky diode d1 (see figure 7). inductor selection chart the chart in figure 11 summarizes the relationship between led current, switching frequency, and inductor value. based on this chart: assuming led current = 2 a and f sw =1 mhz, then the minimum inductance required is l = 10 h in order to keep the ripple current at 30% or lower. (note: v out = v in / 2 is the worst case for ripple current). if the switching frequency is lower, then either a larger inductance must be used, or the ripple current requirement has to be relaxed. figure 11. inductance selection based on i led and f sw ; v in = 24 v, v out = 12 v, ripple current = 30% figure 10. A6211 overcurrent protection tripped in the case of a fault caused by the sense resistor pin shorted to ground; shows switch node, v sw (ch1, 10 v/div.), output voltage, v out (ch2, 10 v/div.), led current, i led (ch3, 1 a/div.), t = 100 s/div. 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 switching frequency, f sw (mhz) led current, i led (a) l=15 h l=22 h l=33 h l=47 h l=10 h t c1 c3 c2 v sw v out i led
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v in sw d1 led+ led? l1 cs . . . i ripple v ripple v ripple r sense v in sw d1 led+ led? l1 cs c1 . . . i ripple r sense figure 12. ripple current and voltage, with and without shunt capacitor without output capacitor: ripple current through led string is proportional to ripple voltage at cs pin. with a small capacitor across led string: ripple current through led string is reduced, while ripple voltage at cs pin remains high. additional notes on ripple current ? for stability, pick the inductor and switching frequency to ensure the lowest inductor ripple current percentage is at least 12.5% during worst case (at the lowest v in ). ? there is no hard limit on the highest ripple current percentage allowed. a 60% ripple current is still acceptable, as long as both the inductor and leds can handle the peak current (average cur- rent 1.3 in this case). however, care must be taken to ensure the valley of the inductor ripple current never drops to zero at the highest input voltage (which implies a 200% ripple current). ? in general, allowing a higher ripple current percentage enables lower-inductance inductors to be used, which results in smaller size and lower cost. the only down-side is the core loss of the inductor increases with larger ripple currents. but this is typically a small factor. ? if lower ripple current is required for the led string, one solu- tion is to add a small capacitor (such as 2.2 f) across the led string from led+ to led? . in this case, the inductor ripple cur- rent remains high while the led ripple current is greatly reduced. output filter capacitor the A6211 is designed to operate without an output filter capaci- tor, in order to save cost. adding a large output capacitor is not recommended. in some applications, it may be required to add a small filter capacitor (up to several f) across the led string (between led+ and led-) to reduce output ripple voltage and current. it is important to note that: ? the effectiveness of this filter capacitor depends on many fac- tors, such as: switching frequency, inductors used, pcb layout, led voltage and current, and so forth. ? the addition of this filter capacitor introduces a longer delay in led current during pwm dimming operation. therefore the maximum pwm dimming ratio is reduced. ? the filter capacitor should not be connected between led+ and gnd. doing so may create instability because the control loop must detect a certain amount of ripple current at the cs pin for regulation.
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 13. waveforms showing the effects of adding a small filter capacitor across the led string ? operating conditions: at 200 hz, v in = 24 v, v out = 15 v, f sw = 500 khz, l = 10 h, duty cycle = 50% ? ch1 (red) = v in (10 v/div), ch2 (blue) = v out (10 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 1 ms/div panel 13a. operation without using any output capacitor across the led string panel 13b. operation with a 0.68 f ceramic capacitor connected across the led string t c1,c2 c3 c4 v in v out i led v en t c1,c2 c3 c4 v in v out i led v en
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application circuit the application circuit in figure 14 shows a design for driving a 15 v led string at 1.3 a (set by r sense ). the switching fre- quency is 500 khz, as set by r1. a 0.68 f ceramic capacitor is added across the led string to reduce the ripple current through the leds (as shown in figure 13b). led+ led? vin ton en cs sw boot gnd vcc A6211 1 2 3 4 8 7 6 5 v in = 24 to 48 v c1 47 f 50 v c2 4.7uf 50v en c4 0.1 f r1 140 k l1 10 h / 2 a c5 0.1 f r sense 0.15 gnd d1 60 v / 2 a c3 0.68 f 50 v led string ( 15 v) ... figure 14. application circuit diagram suggested components symbol part number manufacturer c1 emza500ada470mf80g united chemi-con c2 umk316bj475kl-t taiyo yuden l1 nr8040t100m taiyo yuden d1 b250a-13-f diodes, inc. r sense rl1632r-r150-f susumu
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com component placement and pcb layout guidelines pcb layout is critical in designing any switching regulator. a good layout reduces emitted noise from the switching device, and ensures better thermal performance and higher efficiency. the following guidelines help to obtain a high quality pcb layout. figure 15 shows an example for components placement. figure 16 shows the three critical current loops that should be minimized and connected by relatively wide traces. 1) when the upper fet (integrated inside the A6211) is on, cur- rent flows from the input supply/capacitors, through the upper fet, into the load via the output inductor, and back to ground as shown in loop 1. this loop should have relatively wide traces. ideally this connection is made on both the top (component) layer and via the ground plane. 2) when the upper fet is off, free-wheeling current flows from ground through the asynchronous diode d1, into the load via the output inductor, and back to ground as shown in loop 2. this loop should also be minimized and have relatively wide traces. ideally this connection is made on both the top (component) layer and via the ground plane. 3) the highest di/dt occurs at the instant the upper fet turns on and the asynchronous diode d1 undergoes reverse recovery as shown in loop 3. the ceramic input capacitors c2 must deliver this high instantaneous current. c1 (electrolytic capacitor) should not be too far off c2. therefore, the loop from the ceramic input capacitor through the upper fet and asynchronous diode to ground should be minimized. ideally this connection is made on both the top (component) layer and via the ground plane. 4) the voltage on the sw node (pin 8) transitions from 0 v to v in very quickly and may cause noise issues. it is best to place the asynchronous diode and output inductor close to the A6211 to minimize the size of the sw polygon. keep sensitive analog signals (cs, and r1 of switching fre- quency setting) away from the sw polygon. 6) for accurate current sensing, the led current sense resistor r sense should be placed close to the ic. 7) place the boot strap capacitor c4 near the boot node (pin 7) and keep the routing to this capacitor short. 8) when routing the input and output capacitors (c1, c2, and c3 if used), use multiple vias to the ground plane and place the vias as close as possible to the A6211 pads. 9) to minimize pcb losses and improve system efficiency, the input (vin) and output (vout) traces should be wide and dupli- cated on multiple layers, if possible. figure 16. three different current loops in a buck converter figure 15. example layout for the A6211 evaluation board v in c in c out d1 l1 led sw loop 2 loop 1 loop 3
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 10) to improve thermal performance, use multiple layers for gnd. place as many vias as possible to the ground plane around the anode of the asynchronous diode. 11) the thermal pad under the A6211 must connect to the ground plane using multiple vias. more vias will insure lower operating temperature and higher efficiency. 12) connection to the led array should be kept short. exces- sively long wires can cause ringing or oscillation. when the led array is separated from the converter board and an output capaci- tor is used, the capacitor should be placed on the converter board to reduce the effect of stray inductance from long wires.
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3.30 2 1 8 reference land pattern layout (reference ipc7351 soic127p600x175-9am); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c 1.27 5.60 2.41 1.75 0.65 2.41 nom 3.30 nom c seating plane 1.27 bsc gauge plane seating plane a terminal #1 mark area b c b 2 1 8 c seating plane c 0.10 8x 0.25 bsc 1.04 ref 1.70 max for reference only; not for tooling use (reference ms-012ba) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown 4.90 0.10 3.90 0.10 6.00 0.20 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 8 0 exposed thermal pad (bottom surface); dimensions may vary with device a branded face package lj, 8-pin narrow soic with exposed thermal pad
constant-current 3-ampere pwm dimmable buck regulator led driver A6211 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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